The biggest and best collection of examples of logical elements

More than 130 diagrams,

most of them published here for the first time!

© Copyright Karl Scherer September 2003.

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Basic Elements - Logical Gates - Useful Gadgets - Wire Crossing - Memory (ROM and Flip-Flops) - Edge Detectors - Splitters, Switches, Junctions - Shortening and Lengthening - Shift Register - Mathematical Operations

What is Wireworld?

and was included in his program PHANTOM FISH TANK.

A. K. Dewdney publicized WireWorld in his "Computer Recreations" column (Scientific American, January, 1990).

Like a typical cellular automaton, it consists of coloured square cells laid on a rectangular grid.

The squares change colour according to what their immediate neighbours look like.

The background colour (usually black) stays unchanged, Red ('electron head') turns Blue (electron tail),

Blue turns Yellow (Wire), yellow turns Red if it is adjacent to one or two Reds.

Many new and old examples are given below, including binary adders and binary multipliers.

Can I run it on my computer?

Yes, here are three programs which run Wireworld:

- The Zillions game "Wireworlds" by Karl Scherer includes all the examples given on this web page. The game also allows you to change board setups and the rules. It has the most and best examples, many only found recently.
- The Java applet "Mirek's Cellebration" by Mirek Wójtowicz. This applet plays many different automata, but has only a small collection of (mostly suboptimal) examples of Wireworld gates.
- Mirek's full
Cellebration program (large 4MB program, non-Java, but same examples
as the Java applet)

- Mark Owen
has built a Wireworld computer and some other gadgets.

Some fast clocks

A clock sends out regular signals without receiving any input.

Top: 3-cycle clock; bottom: 4-cycle clock.

Clocks usually consist of a circuit with one or more electrons circling.

but can have other forms as well.

Data-copying and delay

Copying is done simply by having a wire end contacting two wire ends.

The delay is intro duced in the second diagram to keep the data flowing in step

when the parallel wires are guided around corners.

Transit times for data copying: 1 cycle.

Delay of copying process compared to straight wire: 0 cycles

Diodes and transistors

Diodes block the data flow in one direction only.

Datta is blocked in the top diagram and flows freely to the right in the diagram below. .

Transistors control the data flow in a wire.

The first transistor (3rd diagram) blocks the data with an active control line.

This transistor type is also called an ANDNOT gate (see diagram below on ANDNOT gates below).

The transistor below blocks the data with an inactive control line (this is the type used in electronics).

This transistor type is also called an AND gate (see diagram below on AND gates below).

Diode transit time: 3 cycles. Delay compared to straight wire: 0 cycles.

Transistor transit times: 2 and 8 cycles. Delay compared to straight wire: 0 and 3 cycles.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

3-cycle, 4-cycle, 5-cycle, 6-cycle NOT gates

A NOT gate emits an electron if and only if there is no incoming electron.

The 'electron' gun on the left emits electrons and plays
the role of the ("random") input data stream.

Distance between electrons for this gate to operate properly:
multiples of 3, 4, 5, 6 cycles.

(3-cycle gate by Karl Scherer, 4-cycle gate and last two 6-cycle gates by Nyles Heise)

(3-cycle gate by Karl Scherer, 4-cycle gate and last two 6-cycle gates by Nyles Heise)

OR gate

An OR gate emits an electron if there is an incoming electron at one of the two input wires.

This design is appropriate for all n-cycle data, n > 2 !

This OR gate consists of only 5 cells arranged in a cross shape.

A NOR gate can be constructed from an OR gate followed by a NOT gate.

Transit time: 1 cycle. Delay compared to straight wire: 0 cycles.

3-cycle XOR gate (works for any n>2)

by Michael Greene

The XOR has been built from other gates using the fact that

XOR(A,B) = ( A ANDNOT B) OR (B ANDNOT A).

Transit time: 16 cycles.

XOR gates for n > 3

An XOR gate emits an electron if there is an incoming electron at one of the two input wires, but not on both.

Top diagram: Two 4-cycle XOR gates by Nyles Heise (one on each side of the pair of data-producing circuits).

These are the smallest XOR gate for 4-cycle data. Note that the left one of the two works for all n>3 !

(There is a smaller XOR using what Nyles Heise calls 'complex' data, where the zero is represented by a delayed electron;

details see file Heise_Wireworld.zrf in the Zillions game Wireworlds.)

Bottom left : smallest XOR for n-cycle data, n=5 or larger, found by Matthieu Walraet.

Note that its symmetry allows to emit the result to BOTH sides (left output wire not shown here)!

Center: Well-known XOR for n=5 or larger. Right : XOR for n>5, found by Karl Scherer.

AND gate for n = 3

by Karl Scherer

The design for 3-tick data presented here uses the fact that

AND (A,B) = NOT (NAND(A,B)) = NOT ((NOT(A) OR NOT(B))

Transit time: 11 cycles

AND gates for n > 3

An AND gate emits an electron if there are incoming electrons at both input wires.

Top: 4-cycle AND gate by Nyles Heise.

Centre left: an improvement by Karl Scherer on the standard AND gate at the bottom;

works for n > 4.

Bottom right: AND gate for n > 4 by Karl Scherer (based on similar design by Moore/Owen).

It uses the fact that (A and B) = (A andnot (A xor B)).

Top right: a very small design, for n > 5, by Nyles Heise with a transit time of only 6 ticks!

6-cycle AND gates

Top: design by Karl Scherer, transit time = 8

Bottom: design by Nyles Heise, transit time = 10.

ANDNOT gate for n>2

Design by Michael Greene

ANDNOT gates

The ANDNOT gate can be seen as a data-driven NOT gate: ANDNOT(A, B) = AND(A, NOT(B)).

It creates an output only if A is active and B is not.

In this diagram A is always the wire coming from below.

From the top, the diagrams show ANDNOT gates for 4-cycle (2), 5-cycle and 6-cycle data.

The second diagram was found by Nyles Heise.

Note that for 5-cycle and 6-cycle data the gate is very similar to the NOT gate;

we only had to replace the clocked input by a general input wire.

This simple solution does NOT work for 4-cycle data, however.

The combined ANDNOT/OR gates

Such a gate has two outputs:

(A ANDNOT B) at top, (A OR B) at bottom.

Top: Gate works for any n-cycle data with n>3; found by Klaus Mogensen.

Bottom: Gate works only for n-cycle data with n>4; found by David Moore and Mark Owen.

3-cycle NAND gate

by Karl Scherer; using

NAND(A,B)= OR(NOT(A),(NOT(B))

4-cycle NAND gate

by Karl Scherer (based on work by Nyles Heise).

Designs based on the fact that NAND(A,B) = OR(NOT(A), NOT(B)).

5-cycle NAND gates

Top design: smallest, by Karl Scherer.

Bottom: widely publicised, old version.

A NAND gate always emits an electron except when there are incoming electrons at both input wires.

Transit time: 14 and 15 cycles (from straight to straight).

Sizes (without contact wires): 6x11=66 and 7x9 = 72

Delay compared to straight wire: 5 cycles and 4 cycles.

6-cycle NAND gates

A NAND gate always emits an electron except when there are incoming electrons at both input wires.

Top: fastest and smallest NAND gates found by Karl Scherer in 2004.

At size 4x13, transit time is only 3 cycles (left example)!

Bottom left: Improved classic design by Karl Scherer, with a faster transit time that the classic design next to it.

Bottom right: Classic design, widely published.

6-cycle EQUAL gate

An EQUAL gate emits an electron if there are incoming electrons at both input wires

and also if there is no incoming electron on either wire.

To build it, we used the identity EQ(A,B) = XOR(NOT(A),B) .

Transit time: 7 cycles. Delay compared to straight wire: 0 cycles.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

Frequency doublers

Frequency Halvers (delete every 2nd position)

The frequency halver 4 => 8 presented here at the top seems to be new;

I could not find it published anywhere. It is a bit tricky to find because

the trick can only be done with the very unusual asynchronous electrons in the controlling circuit!

This little invention allows us to create ALL LOGIC GATES FOR 4-CYCLE DATA,

again something which seems to be published here for the first time;

see associated images on 4-cycle AND and 4-cycle NOT gates!

(In the other two cases the asynchronous circuit is not essential, but it helps to make the diagram smaller.

Though less important, I have not seen them published either.)

4-cycle Fuse

Design: Karl Scherer

A signal to the fuse will cause it to stop all data flowing.

Depending how long the wire to the transistor (transistors) on the right is being fashioned,

the data will stop only after a certain delay.

5-cycle fuses

Designs: Karl Scherer

A signal to the fuse will cause it to stop all data flowing.

Depending how long the wire to the transistor (transistors) on the right is being fashioned,

the data will stop only after a certain delay.

Two 6-cycle fuses

A signal to the fuse will cause it to stop all data flowing.

Depending how long the wire to the transistors on the right is being fashioned,

the data will stop being allowed thorugh only after a certain delay.

The top fuse has a faster throughput than the lower fuse.

3-cycle wire crossing

by Nyles Heise

using three 6-cycle wire crossings.

Transit time: 37 cycles

n-cycle wire crossing for all n>3

by Klaus Mogensen

4-cycle wire crossing

by Nyles Heise.

Size 9x14, transit time 8 cycles.

Wire crossings for n > 4 (left, centre) and n > 5 (on the right)

Left: classic design for n>4.

Centre: new, smaller design by Karl Scherer for n>4 (based on Walraet's XOR).

Right: new, smaller design for n>5 by Karl Scherer.

Transit time: 9, 9, and 8 cycles. Sizes: 9x13, 8x13 and 8x13.

Delay compared to straight wire: 0 cycles.

6-cycle wire crossing

by Karl Scherer, based on 3-cycle data splitter.

Crossing works only for n = 6m.

8-cycle wire crossing

Design: Karl Scherer

Amazingly, this simple wire-crossing seems to be new.

It is a bit tricky to find, because it uses two asynchronous electrons in each of its controlling circuits.

These circuits are used to split the output of the OR gate, a 4-cycle data stream, into two 8-cycle data streams.

This design is smaller than the standard wire crossing with three XOR gates (see above)

and hence preferrable for 8-cycle data.

Transit time : 10. Size : 6x14. Delay compared to straight wire: 4 cycles.

Asynchronous Wire Crossings for n>4

All by Karl Scherer except the one on bottom left, which is by Mark/Owens

These four crossings only work when data do not arrive simultaneously on both inpout wires.

Special Wire Crossing (A,B) => (B and A, A)

Very useful for some applications, because smaller than the standard wire-crossing above.

Disadvantage : Data from B is not crossing, only AND(A,B) gets through.

Transit time: 11 cycles. Distance between data >4 cycles.

Delay compared to straight wire: 2 cycles.

Special wire crossing (A,B) => (B andnot A, A andnot B)

Design by David Moore and Mark Owen

Works as crossing as long as A and B do not fire at the same time.

Example for application: see chapter on ROM (read-only memory).

Distance between data >4 cycles.

Delay compared to straight wire: 0 cycles.

Reflector

A detector together with an OR gate in a litle loop serves as a reflector for a single electron.

The lower diagram will create two electrons which race back and forth and change direction at the centre.

I could not find any other use for reflectors.

In read-only memory the data cannot be changed, but it can be read.

ROM

Design by David Moore and Mark Owen

Several combined ANDNOT/OR gates can be arranged in a rectangular pattern to form a read-only memory.

Here we have three input lines, each associated with four stored bits.

The bits are those gates that have a missing 'ear'.

An incoming electron moves toward the top right.

Whenever the electron encounters a stored bit, it creates a twin.

This twin then travels towards the bottom right, where it exits.

The first electron will create output in the top two lines, the second electron will create bits in the bottom three output lines.

Check how this corresponds to the missing 'ears' of the gates.

A rectangular grid of 10x7 gates can be used to convert data from ten input lines

(carrying bits representing the digits 0 to 9) into a data stream for a digital display (LCD) consisting of 7 elements.

The gadget works for n-cycle data with n>4.

A flip-flop is a bi-stable circuit.

This chapter covers mono-input flip-flops and dual-input flip-flops.

On the first input signal, it regularly outputs signals;

on the next input signal it stops sending signals.

The 7-cycle flip-flop is the smallest mono-input flip-flop overall. It consists of only 15 cells!

Transit times are calculated from the end of the input wire to the beginning of the output wire.

3-cycle flop-flops

Top: by Karl Scherer Nov 2004

Bottom: by Nyles Heise Nov 2004

Sizes: 18x18 and 13x24; Transit time: 22 and 30 cycles.

Note that the first (slightly larger) design has a much faster transit time!

Mono-input flip-flops for n-cycle data, n = 4, 6, 8,...

Design by Nyles Heise.

Nyles's flip-flops are the smallest known flip-flops for n = 4 and n = 6.

by Karl Scherer (based on Nyles Heise's 4-cycle flip-flop).

Similar constructions are possible for any n-cycle data, n odd.

Mono-input flip-flops for n-cycle data, n = 8, 10, 12,....

Design by Karl Scherer.

Note that none of these flip-flops use an internal clock.

Karl's flip-flops are the smallest known flip-flops for n > 6.

Similar flip-flops can be constructed for any even n > 12.

Mono-input flip-flops for n-cycle data, n = 7, 11, 13,....

Design by Karl Scherer.

Similar flip-flops can be constructed for any odd n > 11.

Karl's flip-flops are the smallest known flip-flops for n > 6.

Note that none of these flip-flops use an internal clock!

Top: smallest 5-cycle flip-flop

Middle: 6-cycle flip-flops (left: classic design; symmetric one on right by Matthieu Walraet)

Right: This 7-cycle flip-flop is the smallest of all flip-flops by Matthieu Walraet.

Bottom: smallest 12-cycle flip-flop.

3-cycle dual-input flip-flop (RS-latch)

by Michael Greene

Size: 7x8; Transit time: 8 cycles.

Dual-input flip-flop (4-cycle data)

by Nyles Heise

Reset-dominant (here reset-signal at top).

Also called 'reset-domionant RS-latch'.

dual-input 5-cycle flip-flop

Design: Karl Scherer

Note that it uses a special crossover that was also invented by Karl Scherer.

Since a 5-cycle loop cannot be constructed, a trick is needed to make the flip-flop possible:

the design uses a 10-cycle loop (seen at the top right)

with two synchronous input lines and two synchronous ANDNOT gates.

Hence the loop always carries two electrons or none at all.

Start-signal at bottom, stop-signal coming in from left.

dual-input 5-cycle flip-flop (asynchronous)

Design: Karl Scherer

The flip-flop displayed here only works when the two input data never arrive at the same time, hence when they are asynchronous.

The flip-flip will, however, tolerate stop-signals while the flip-flop is stopped already and also start-signals arriving when the flip-flop is running already.

How does it work?

The small 10-cycle loop at the top right always carries either two electrons or none at all.

To start the cycle, two electrons are inserted at opposite corners of this loop.

To stop the cycling, the two electrons are stopped by two gates, both at the same time.

Hence the stop-signal coming from the stop-loop at the left must supply two gates

and hence must cross at least one of the two start-signal lines, which come from the start-loop at the bottom.

For this reason we use a simple cross-over (A,B) => (B not A, A not B).

Advantage to the flip-flop in the previous variant: Faster transition time and smaller design.

Disadvantage: only works with asynchronous data.

Dual-input flip-flops (6-cycle data)

Also called 'RS-latches' (Reset-Set Latches).

Set-impulse arrive from left, reset bits from right.

Latches shown are reset-dominant.

However, the middle and bottom examples let always the first set-bit pass.

(This can be avoided by inserting an additional NOT-gate, as done in the top flip-flop).

The flip-flop at the bottom lets inappropriate stop-signals pass, hence is only useful if

it is guaranteed that a stop-signal is only issued when the flip-flop is active.

It has no advantage over the top flip-flop.

The middle diagram avoids this problem, but at the price of space and complexity.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

Positive-edge detectors for n = 4, 5, 6

A positive-edge detector emits a signal when it finds the first One (electron) in a row of Ones.

It is easy to see how similar edge detectors can be built for any n.

Negative-edge detectors

A negative-edge detector emits a signal when it finds the first Zero (missing electron)

after a series of Ones.

The top diagram shows an example for 5-cycle data, the lower diagram one for 6-cycle data.

5-cycle and 6-cycle double-edge detectors

A double-edge detector emits a signal when it finds the first (One) of a string of consecutive electrons

and it emits a signal when it find the first gap (Zero).

Reconstructing a data from its edges (6-cycle data)

Block only the second electrons in any consecutive string of electrons (6-cycle data)

by Karl Scherer

Note the extreme simplicity of the design.

Transit time: 7 cycles; Size: 7x9.

Delete every third position of a adata stream.

Note how extremely small the gates are for 4-cycle and 5-cycle data.

For 6-cycle data we have to use a standard clock-type control.

001-detector (6-cycle data)

Note the extreme simplicity of the design.

Transit time: 7 cycles; Size: 8x8.

010-detector (solitair-electron detector for 6-cycle data)

by Karl Scherer

A 010-pattern in a data stream means that an electron (One) is not preceded or followed by another electron (One).

The 010-detector is the part attached to the vertical wire on the left;

here its output is used to eliminate solitair electrons (via the transistor on the right).

Transit time: 14 cycles; Size: 8x10.

Gap-Filler (6-cycle data)

This little tool fills up any solitair gaps.

In other words, it replaces any 101-pattern by a 111-configuration.

(Note, however, that it is NOT a 101-detector, since it does not see the difference between 101 and 111)

Transit time: 20 cycles; Size 8x13 .

Transit times are calculated from the end of the input wire to the beginning of the output wire.

Designs by Karl Scherer

The data is directed to a different output wire after every third cycle.

4-cycle and 5-cycle data splitters

Constructed using two frequency halvers.

The data is directed to a different output wire after every fourth (fifth) cycle.

Similar splitters can be easily constructed for any data types.

Controlled data copier (normal and externally controlled)

One output wire carries the original data, whereas a second output wire carries copies of this data only if the control line is active.

In the example at the top, the through-wire is at the bottom and the top output line is controlled.

As you can see in the second example, the task is a bit more tricky when controlling wire and controlled wire are on opposite sides of the through-wire.

In such a case (where we use the "special wire crossing"!) , we call the data "externally controlled".

Externally controlled switch (De-Multiplexer) for n>4

by Karl Scherer

The input data are directed to the lower output wire when the control line is active;

otherwise it is directed to the upper output line.

The control would be easier if it would be situated

in between the two output wires (because no wire crossing necessary).

Note again how we have avoided here the use of the standard (and bulky) "wire crossing" gadget.

Externally triggered switch

by Karl Scherer

Same as above, but only one electron is necessary to connect the input data

long term to one of the output wires.

Externally controlled junction (Multiplexer)

by Karl Scherer

A control wire joins one of two, but never both, input wires to a single output wire.

3-cycle Data-driven Splitter

by Karl Scherer

Each incoming electron is being directed to another output wire.

Size: 29x47; Transit time: 73 cycles.

5-cycle Data-driven Splitter

by Karl Scherer

Each incoming electron is being directed to another output wire.

Distances are conserved; therefore we can join the results to recreate the original input.

6-cycle Data-driven Splitters

by Karl Scherer

Each incoming electron is being directed to another output wire.

Distances are conserved; therefore we can join the results to recreate the original input.

Note that the example on the left is based on a external-triggered switch.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

Lengthening and shortening-at-end

by Karl Scherer

The setup demonstrates lengthening and shortening of strings for 5-cycle data (outer ring) and for 6-cycle data.

The shortening part eliminates the last electron in a sequence.

Transit times: lengthening 5 cycles, shortening 14 (15) cycles.

Delay compared to straight wire: lengthening 0, shortening 5 (6) cycles.

Lengthening and shortening-at-start

by Karl Scherer

The setup demonstrates lengthening and shortening of strings of consecutive 5-cycle electrons.

The lengthening uses a negative-edge-detector.

The shortening part eliminates the first electron in a sequence.

Transit times: lengthening 5 cycles, shortening 10 cycles.

Delay compared to straight wire: lengthening 0, shortening 1 cycle.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

Shift Register

by Karl Scherer

A shift register activates a series of memory cells one by one.

\Only one memory cell (= register) is active at any time.

A shift register is also called 'serial to parallel converter', because the first signal is directed to the first output wire,

the second signal to the second output wire and so on. (In our diagram, the 'first output wire' is the second from the top).

After the last memory cell has been activated, the process starts all over with the first memory cell being activated.

Details: The diagram shows a 5-bit shift register for 6-cycle data. For the memory we use dual-input flip-flops.

Any input signal stops all flip-flops from working. This causes - via the negative edge detectors - the next flip-flop to start up.

Positive edge detectors make sure that each flip-flop sends only one signal down its output wire.

If you want the flip-flops to fire as long as they are active, delete the positive edge detectors.

Note the compactness of the construction.

Transit times are calculated from the end of the input wire to the beginning of the output wire.

"Binary Counter" (using Flip-Flops as indicators)

Input: one string of consecutive electrons representing a number

Output: a series of active or inactive flip-flips, representing a binary number.

Binary Counter

by Karl Scherer

Input: uninterrrupted sequence of n electrons

Output: data stream representing n as a binary number. The top loop tells us where the smallest digit is.

This is a simple applications of the Binary Adder gadget, see below.

Transit time: n rounds, one per given electron.

Primitive multiplier

by Karl Scherer

Input: two strings of n and m consecutive electrons, respectively

Output : n*m electrons (containing some gaps in the string)

True binary adder for n=4

by Klaus Mogensen

True binary adder for n=5

by Klaus Mogensen

Smallest true binary adder for n=6

by Tony Ennis

Set up to calculate 6+5=11

True binary adder for n=6

by Klaus Mogensen

True binary adders for n=4 and n=6

Designs: Top: Karl Scherer (n=4; based on adder for n=6)

Bottom : David Moore and Mark Owen (improved by Karl Scherer).

The top adder uses 4-cycle data and is set up to add 1+3 = 4.

The bottom adder uses 6-cycle data and is set up to add 3+2 = 5.

In both cases the top input is copied undisturbed for convenience: it makes it easier to find the

position of the lowest digit in the output. We call the top input B and the bottom input A.

Then the XOR at the left side has the output (A xor B).

At the lower left we see an ANDNOT gate with the output ANDNOT (A, AxorB) = AND(A,B),

which is the carry bit. This carry bit feeds a dual-input flip-flop.

(Note that the top adder uses a special 4-cycle flip-flip not mentioned in any other chapter here;

it always lets the incoming bit through, which a flip-flop normally is not allowed to do.)

The carry bit is always allowed to move on towards the final XOR gate, where

it is XORed with the following (A xor B) bit, resulting in zero if A or B are firing.

The carry bit is also stored in the flip-flop as long as (A xor B) blocks the NOT gate.

It is released as soon as (A xor B) = 0, hence when A=B=0 or when A=B=1.

This are exactly the cases when the adding of the carry bit is wanted.

The adder structure described here is called a `propagate-generate adder':

A AND B generates a carry from the current bit, and A XOR B propagates a carry through it

Many fast adders implemented on real integrated circuits use exactly this technique.

The simpler `ripple carry' structure, where each bit explicitly computes sum and carry outputs as direct functions

of its inputs A and B and the carry output from the previous bit, are generally slower.

Transit time: 27 and 19 cycles

Size of adder : 19x27 and 17x19

True Binary Adder for n=5

Design: Karl Scherer (based on the Moore/Owen adder for n=6)

Note that the adder uses a dual-input 5-cycle flip-flop which also has been invented by Karl Scherer.

True binary adder for n=6

by Karl Scherer

It adds two binary numbers of any size (if input wires made long enough).

This is most probably the smallest binary adder possible in Wireworld.

Input: two data streams representing binary numbers n and m (1 = electron, 0 = no electrons, intervals = 6 cycles)

Output : one data stream representing a binary number n+m; the top loop tells us where the smallest digit of the result is.

Transit time: 48 cycles Size: 20x29

True binary multiplier (6-cycle data)

by Karl Scherer

This is most probably the smallest binary multiplier possible in Wireworld.

The center lines show the numbers ('11' = 3 and '101' = 5) to be multiplied.

The line underneath them will show the result ('1111' = 15) after 132*3 = 396 cycles..

Input: two data streams representing binary numbers n and m (1 = electron, 0 = no electrons, intervals = 6 cycles)

Output : one data stream representing a binary number n*m; the top loop tells us where the smallest digit of the result is.

Transit time*: 132*(d+1) cycles, where d is the number of digits in n. Size: 49x49

*If large input numbers are given, then several of the wires have to be lengthened

and the transit time factor will be larger than 132.

True binary multiplier (4-cycle data)

by Nyles Heise

Multiplies two 6-bit numbers
giving a 12-bit product.

C = A * B

There are 6 components in the multiplier

1) Clock, top left, 44 cells

2) Multiplicand A, next on left, 20 cells.

High order bit enters the multiplier first. First bit is actually outside the loop.

3) Multiplier B, next on left, 44 cells. Low order bit first.

4) Product C, bottom left, 48 cells

C = A * B

There are 6 components in the multiplier

1) Clock, top left, 44 cells

2) Multiplicand A, next on left, 20 cells.

High order bit enters the multiplier first. First bit is actually outside the loop.

3) Multiplier B, next on left, 44 cells. Low order bit first.

4) Product C, bottom left, 48 cells

In expanded version the loop is extended to better show

the final result, which appears in 334 cycles

(i.e., when the electron in the big loop at left is back to the white dot).

5) Full Adder, bottom right

6) Gate, top right - a latch that allows B to FA when

corresponding bit of A is a 1

The diagram is set up to do (binary 11111 * 11111 =) 63*63 = 3969 (= 1111 1000 0001 in binary)

the final result, which appears in 334 cycles

(i.e., when the electron in the big loop at left is back to the white dot).

5) Full Adder, bottom right

6) Gate, top right - a latch that allows B to FA when

corresponding bit of A is a 1

The diagram is set up to do (binary 11111 * 11111 =) 63*63 = 3969 (= 1111 1000 0001 in binary)